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technical note high-performance regulator ic series for pcs ultra low dropout linear regulators for pc bd3550hfn, bd3551hfn, bd3552hfn (0.5 2.0a) description bd3550hfn,bd3551hfn,bd3552hfn ultra low-dropout linear chip set regulator operates from a very low input supply, and offers ideal performance in low input voltage to low output vo ltage applications. it incorporates a built-in n-mosfet power transistor to minimize the input-to-output vo ltage differential to the on resistance (r on =100m ) level. by lowering the dropout voltage in this way, the regulator realizes high current output (iomax=2.0a ) with reduced conversion loss, and thereby obviate s the switching regulator and its power transistor, choke coil, and rectifier diode. thus, bd3550hfn,bd3551hfn,bd3552hfn is designed to enable significant package profile downsizing and cost reduction. an external resistor allows the entire range of output voltage configurations between 0.65 and 2.7v, while the nrcs (soft start) function enables a controlled output volt age ramp-up, which can be programmed to whatever power supply sequence is required. features 1) internal high-precision reference voltage circuit(0.65v 1%) 2) built-in vcc undervoltage lockout circuit 3) nrcs (soft start) function reduces the magnitude of in-rush current 4) internal nch mosfet driver offers low on resistance (100m ) 5) built-in current limit circuit 6) built-in thermal shutdown (tsd) circuit 7) variable output (0.65 2.7v) 8) small package hson8 : 2.9 3 0.6(mm) 9) tracking function applications notebook computers, desktop computer s, lcd-tv, dvd, digital appliances line-up it is available to select power supply voltage and maximum output voltage. maximum output voltage package vcc=5v 0.5a hson8 bd3550hfn 1.0a bd3551hfn 2.0a bd3552hfn oct. 2008
2/16 absolute maximum ratings bd3550hfn,bd3551hfn,bd3552hfn parameter symbol limit unit bd3550hfn bd3551hfn bd3552hfn input voltage 1 vcc +6.0 * 1 v input voltage 2 vin +6.0 * 1 v enable input voltage ven -0.3 +6.0 v power dissipation 1 pd1 0.63 * 2 w power dissipation 2 pd2 1.35 * 3 w power dissipation 3 pd3 1.75 * 4 w operating temperature range topr -10 +100 storage temperature range tstg -55 +150 maximum junction temperature tjmax +150 *1 should not exceed pd. *2 reduced by 5.04mw/ for each increase in ta R 25 (when mounted on a 70mm 70mm 1.6mm glass-epoxy board, 1-layer) on less than 0.2% (percentage occupied by copper foil. *3 reduced by 10.8mw/ for each increase in ta R 25 (when mounted on a 70mm 70mm 1.6mm glass-epoxy board, 1-layer) on less than 7.0% (percentage occupied by copper foil. *4 reduced by 14.0mw/ for each increase in ta R 25 (when mounted on a 70mm 70mm 1.6mm glass-epoxy board, 1-layer) on less than 65.0% (percentage occupied by copper foil.
3/16 bd3550hfn,bd3551hfn,bd3552hfn operating voltage(ta=25 ) parameter symbol min. max. unit input voltage 1 vcc 4.3 5.5 v input voltage 2 vin 0.95 vcc-1 * 5 v output voltage setting range vo vfb 2.7 v enable input voltage ven 0 5.5 v nrcs capacity cnrcs 0.001 1 f *5 vcc and vin do not have to be implemented in the order listed. this product is not designed for use in radioactive environments. electrical characteristics (unless otherwise specified, ta=25 , vcc=5v, ven=3v, vin=1.8v, r1=3.9k , r2=3.3k ) parameter symbol limit unit condition min. typ. max. bias current icc - 0.5 1.0 ma vcc shutdown mode current ist - 0 10 ua ven=0v output voltage vout - 1.200 - v output voltage temperature coefficient tcvo - 0.01 - %/ feedback voltage 1 vfb1 0.643 0.650 0.657 v feedback voltage 2 vfb2 0.637 0.650 0.663 v tj=-10 to 100 load regulation reg.l - 0.5 10 mv io=0 to 1a (bd3550hfn io=0a to 0.5a) line regulation 1 reg.l1 - 0.1 0.5 %/v vcc=4.3v to 5.5v line regulation 2 reg.l2 - 0.1 0.5 %/v vin=1.2v to 3.3v standby discharge current iden 1 - - ma ven=0v, vo=1v [enable] enable pin input voltage high enhi 2 - - v enable pin input voltage low enlow 0 - 0.8 v enable input bias current ien - 7 10 a ven=3v [feedback] feedback pin bias current ifb -100 0 100 na [nrcs] nrcs charge current inrcs 14 20 26 a vnrcs=0.5v nrcs standby voltage vstb - 0 50 mv ven=0v [uvlo] vcc undervoltage lockout threshold voltage vccuvlo 3.5 3.8 4.1 v vcc:sweep-up vcc undervoltage lockout hysteresis voltage vcchys 100 160 220 mv vcc:sweep-down [amp] gate source current i gso - 1.6 - ma v fb =0, v gate =2.5v gate sink current i gsi - 4.7 - ma v fb =vcc, v gate =2.5v maximum output current bd3550hfn io 0.5 - - a bd3551hfn io 1.0 - - a bd3552hfn io 2.0 - - a minimum dropout voltage bd3550hfn dvo - 200 300 mv io=0.5a, vin=1.2v, ta=-10 to 100 bd3551hfn dvo - 200 300 mv io=1.0a, vin=1.2v, ta=-10 to 100 bd3552hfn dvo - 200 300 mv io=2.0a, vin=1.2v, ta=-10 to 100
4/16 reference data (bd3550hfn) reference data (bd3551hfn) fig.1 transient response (0 0.5a) co=100 f, cfb=1000pf fig.2 transient response (0 0.5a) co=47 f, cfb=1000pf fig.3 transient response (0 0.5a) co=22 f, cfb=1000pf fig.4 transient response (0.5 0a) co=100 0a) co=47 f, cfb=1000pf 26mv 0.5a vo 50mv/di v io 0.5a/di v 22mv 0.5a vo 50mv/di v io 0.5a/di v 40mv 0.5a vo 50mv/di v io 0.5a/di v vo 50mv/di v io 0.5a/di v 14mv 0.5a io=0a 1a/ sec t(10 sec/div) io=0a 1a/ sec t(10 sec/div) io=0a 1a/ sec t(10 sec/div) io=1a 0a/ sec t(100 sec/div) 23mv 0.5a io=1a 0a/ sec t(100 sec/div) 33mv 0.5a io=1a 0a/ sec t(100 sec/div) fig.6 transient response (0.5 0a) co=22 f, cfb=1000pf fig.7 transient response (1.0 0a) co=100 1.0a) co 47 1a/ sec t(10 sec/div) io=0a 1a/ sec t(10 sec/div) fig.9 transient response (0 1.0a) io=0a 1a/ sec t(10 sec/div) 55mv 1.0a 36mv 1.0a fig.10 transient response (1.0 0a) co=100 f, cfb=1000pf io=1a 0a/ sec t(100 sec/div) io=1a 0a/ sec t(100 sec/div) 1.0a 46mv io=1a 0a/ sec t(100 sec/div) fig.12 transient response (1.0 0a) co=22 f, cfb=1000pf 56mv 1.0a fig.11 transient response (1.0 0a) co=47 f, cfb=1000pf vo 50mv/div io 0.5a/div vo 50mv/div io 0.5a/div vo 50mv/div io 1.0a/div vo 50mv/di v io 1.0a/di v io=0a 1a/ sec t(10 sec/div) io=0a 1a/ sec t(10 sec/div) fig.7 transient response (0 1.0a) co=100 f, cfb=1000pf fig.8 transient response (0 1.0a) co=47 f, cfb=1000pf vo 50mv/div io 1.0a/div vo 50mv/div io 1.0a/div vo 50mv/di v io 1.0a/di v fig.9 transient response (0 1.0a) co=22 f, cfb=1000pf
5/16 reference data (bd3552hfn) reference data (bd3551hfn) vnrcs 2v/di v vo 1v/di v fig.19 waveform at output start fig.20 waveform at output off fi g .21 in p ut se q uence fig.22 input sequence fig.23 input sequence fig.24 input sequence ven 2v/di v ven 2v/di v t(200 sec/div) t(2msec/div) vcc ven vin vo vcc vin ven vin vcc ven ven vcc vin vcc ven vin vnrcs 2v/div vo 1v/di v vo 50mv/di v io 2.0a/di v fig.13 transient response (0 2.0a) co=100 f, cfb=1000pf io=0a 1a/ sec t(10 sec/div) fig.14 transient response (0 2.0a) co=47 f, cfb=1000pf io=0a 1a/ sec t(10 sec/div) 26mv 2.0a 89mv 2.0a 117mv 2.0a fig.15 transient response (0 2.0a) co=22 f, cfb=1000pf io=0a 1a/ sec t(10 sec/div) vo 50mv/di v io 2.0a/di v fig.16 transient response (2.0 0a) co=100 0a/ sec t(100 sec/div) 54mv 2.0a fig.17 transient response (2.0 0a) co=47 f, cfb=1000pf io=1a 0a/ sec t(100 sec/div) 83mv 2.0a io=1a 0a/ sec t(100 sec/div) fig.18 transient response (2.0 0a) co=22 f, cfb=1000pf 117mv 2.0a vo 50mv/di v io 2.0a/di v vo 50mv/di v io 2.0a/di v vo 50mv/di v io 2.0a/di v vo 50mv/di v io 2.0a/div vcc ven vin vo vcc ven vin vo vcc ven vin vo
6/16 reference data (bd3551hfn) fig.31 ta-iinstb 1.15 1.17 1.19 1.21 1.23 1.25 -101030507090 ta( ) vo(v) fig.25 input sequence fig.26 input sequence vcc ven vin vo vin ven vcc ven vin vcc fig.27 ta-vo (io=0ma) fig.28 ta-icc 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 -10 10 30 50 70 90 ta( ) icc(ma) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -60 -30 0 30 60 90 120 150 ta( ) icc(ua) fi g .29 ta-istb 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 -101030507090 ta( ) iin(ma) fig.30 ta-iin 0 5 10 15 20 25 30 -60 -30 0 30 60 90 120 150 ta( ) iin(ua) 15 16 17 18 19 20 21 22 23 24 25 -101030507090 ta( ) inrcs(ua) fig.32 ta-inrcs -20 -15 -10 -5 0 5 10 15 20 -10 10 30 50 70 90 ta( ) ifb(na) fig.33 ta-ifb fig.34 ta-ien 0 1 2 3 4 5 6 7 8 9 10 -101030507090 ta( ) ien(ua) fig.35 ta-ron (vcc=5v/vo=1.2v) fig.36 vcc-ron 100 100 100 100 100 100 90 100 110 120 130 140 150 2468 vcc(v) ron(m ) 90 100 110 120 130 140 150 -10 10 30 50 70 90 ta( ) ron(m ) 100 vcc ven vin vo
7/16 block diagram pin layout pin no. pin name pin function 1 vcc power supply pin 2 en enable input pin 3 gate gate pin 4 vin input voltage pin 5 vo output voltage pin 6 fb reference voltage feedback pin 7 nrcs in-rush current protection (nrcs) capacitor connection pin 8 gnd ground pin reverse fin connected to heatsink and gnd pin function table hson8 reference block thermal shutdown nrcs current limit cl uvlo tsd en vcc uvlo vcc cl en vcc vcc vin vo fb gate gnd nrcs vo vin tsd 0.13 + 0.1 ? 0.05 4 3 2 1 5 6 7 8 3 . 0 0 0 . 2 2 . 8 0 0 . 2 2 . 9 0 0 . 2 0 . 4 7 5 0 . 3 2 0 . 1 0 0 . 6 5 0.6max. 1 2 3 4 ( 0 . 2 ) ( 1 . 8 ) ( 0 . 2 ) ( 0 . 3 0 ) ( 0 . 0 5 ) ( 2 . 2 ) ( 0 . 1 5 ) ( 0 . 4 5 ) 8 7 6 5 () b d 3 5 5 x lot no. 1pin mark
8/16 operation of each block ? amp this is an error amp that compares the reference volt age (0.65v) with vo to drive the output nch fet (ron=100m :bd3552hfn). frequency optimization helps to realize rapid transient response, and to support the use of ceramic capacitors on the output. amp input voltage ranges from g nd to 2.7v, while the amp output ranges from gnd to vcc. when en is off, or when uvlo is active, output g oes low and the output of t he nchfet switches off. ? en the en block controls the regulator?s on/off state via the en logic input pin. in the off position, circuit voltage is maintained at 0 a, thus minimizing current consum ption at standby. the fet is switched on to enable discharge of the nrcs pin vo, thereby draining the excess charge and prevent ing the ic on the load side from malfunctioning. since no electrical connection is required (e.g., between the vcc pin and the esd prevention diode), module operation is independent of the input sequence. ? uvlo to prevent malfunctions that can occur during a momentary decrease in vcc, the uvlo circuit switches the output off, and (like the en block) discharges nrcs and vo. once the uv lo threshold voltage (typ3. 80v) is reached, the power-on reset is triggered and output continues. ? current limit when output is on, the current limit functi on monitors the internal ic output current against the parameter value (2.0a or more:bd3552hfn). when current exceeds this level, the current limit module lowers the output current to protect the load ic. when the overcurrent state is eliminated, output voltage is restored to the parameter value. ? nrcs (non rush current on start-up) the soft start function enabled by connecting an external capacitor between the nrcs pin and ground. output ramp-up can be set for any period up to the time the nrcs pin reaches vfb (0.65v). during startup, the nrcs pin serves as a 20 a (typ) constant current source to charge the external capa citor. output start time is calculated via formula (1) below. tracking sequence is available by connec ting the output voltage of external power supply instead of external capacitor. and then, ratio-metric sequence is also available by changing the resi stor division ratio of external power supply output voltage. (see the next page) ? tsd (thermal shut down) the shutdown (tsd) circuit automatically switches output off when the chip tem perature gets too high, thus serving to protect the ic against ?thermal runaway? and heat damage. because the tsd circuit is provided to shut down the ic in the presence of extreme heat, in order to avoi d potential problems with the tsd, it is cr ucial that the tj (max) parameter not be exceeded in the thermal design. ? vin the vin line acts as the major current supply line, and is c onnected to the output nchfet drain. since no electrical connection (such as between the vcc pin and the esd protection dio de) is necessary, vin operat es independe nt of the input sequence. however, since an output nchfet body diode exists between vin and vo, a vin-vo electric (diode) connection is present. note, therefore, that when output is sw itched on or off, reverse curr ent may flow to vin from vo. t = c ??? (1) 20 a 0.65v
9/16 timing chart en on/off vcc on/off tracking sequence vin vcc en nrcs vo vin vcc en nrcs vo t t startup hysteresis uvlo startup 0.65v(typ) 0.65v(typ) 1.8v output 1.2v output (r 1 =3.9k , r 2 =3.3k ) tracking sequence 1.8v 1.2v ratio-metric sequence nrcs fb v0 vo r 2 r 1 3.3k 1.2v 3.9k dc/dc 1.8v
10/16 evaluation board component rating manufacturer product name component rating manufacturer product name u1 - rohm bd355xhfn c2 22uf kyocera cm32x5r226m10a c1 1uf murata grm188b11a105kd c13 1000pf murata grm188b11h102kd c10 0.01uf murata grm188b11h103kd r1 3.9k rohm mcr03ezpf3301 r8 0 - jumper r2 3.3k rohm mcr03ezpf3901 c5 22uf kyocera cm32x5r226m10a bd3550hfn,bd3551hfn,bd3552hfn evaluation board schematic bd3550hfn,bd3551hfn,bd3552hfn evaluation board layout (2nd layer and 3rd layer is gnd line.) bd3550hfn,bd3551hfn,bd3552hfn evaluation board standard component list top layer bottom layer silkscreen u1 bd355xhfn (hson8) 1 2 3 4 8 7 6 5 vcc vcc vcc gnd gnd tp1 vo nrcs gnd fb gate vin r4 r8 r1 r2 c5 c6 c8 c9 r3 r7 r6 r5 u2 sw1 c2 c3 c7 c4 c11 c12 c1 en c10 7 5 6 8 4 3 2 1 gnd_s vo_s gnd gnd gnd c13 gnd tp2 vcc jpf2 jpf1 r9 c14 2 3 4 5 vin_s u3 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd
11/16 recommended circuit example component recommended value programming notes and precautions r1/r2 3.9k/3.3k ic output voltage can be set with a conf iguration formula using the values for the internal reference output voltage (v fb )and the output voltage resistors (r1, r2). select resistance values that will avoid the impact of the vref current ( 100na). the recommended total resistance value is 10k . c3 22 f to assure output voltage stability, please be certain the vo1, vo2, and vo3 pins and the gnd pins are connected. out put capacitors play a role in loop gain phase compensation and in mitigating output fluctuation during r apid changes in load level. insufficient capacitance may cause oscillation, while high equivalent series reisistance (esr) will exacerbate output voltage fluc tuation under rapid load change conditions. while a 22 f ceramic capacitor is recomended, actual stab ility is highly dependent on temperature and load conditions. also, note that connecting different types of capacitors in series may result in insufficient total phase compens ation, thus causing oscillation. in light of this information, please confirm operation across a variety of temperature and load conditions. c1 1 f input capacitors reduce the output impedance of the volt age supply source connected to the (vcc) input pins. if the impedance of this power supply were to increase, input voltage (vcc) could become unstable, leading to oscillation or lowered ripple rejection function. while a low-esr 1 f capacitor with minimal susceptibility to temperature is recommended, stability is highly dependent on the input power supply characteristics and the substrate wiring pattern. in light of this information, please confirm operation across a variety of temperature and load conditions. c2 22 f input capacitors reduce the output impedance of the volt age supply source connected to the (vin) input pins. if the impedance of this po wer supply were to increase, input voltage (vin) could become unstable, leading to oscillation or lowered ripple rejection function. while a low-esr 22 f capacitor with minimal susceptibility to temperature is recommended, stability is highly dependent on the input power supply characteristics and the substrate wiring pattern. in light of this information, please confirm operation across a variety of temperature and load conditions. c4 0.01 f the non rush current on startup (nrcs) func tion is built into the ic to prevent rush current from going through the load (vin to vo) and impacting output capacitors at power supply start-up. constant current comes fr om the nrcs pin when en is high or the uvlo function is deactivated. the temporar y reference voltage is proportionate to time, due to the current charge of the nrcs pin ca pacitor, and output voltage start-up is proportionate to this reference voltage. capa citors with low susceptibility to temperature are recommended, in order to assure a stable soft-start time. c5 - this component is employed when the c3 capa citor causes, or may cause, oscillation. it provides more precise internal phase correction. r4 several k several 10k it is recommended that a resistance (several k to several 10k ) be put in r4, in case negative voltage is applied in en pin. 1 2 3 4 8 7 6 5 vout1(1.2v) c3 r2 r1 fb c4 gnd vcc c1 en c2 vin r4 c5
12/16 heat loss thermal design should allow operation within the following condi tions. note that the temper atures listed are the allowed temperature limits, and thermal design should allow sufficient margin from the limits. 1. ambient temperature ta can be no higher than 100 . 2. chip junction temperature (tj) can be no higher than 150 . chip junction temperature can be determined as follows: it is recommended to layout the via for heat radiation in the gnd pattern of reverse (of ic) when there is the gnd pattern in the inner layer (in using multiplayer substrat e). this package is so small (size: 2.9mm 3.0mm) that it is not available to layout the via in the bottom of ic. sp reading the pattern and being increased the number of via like the figure below). enable to get the superior heat radiation characteristic. (thi s figure is the image. it is reco mmended that the via size and the number is designed suitable for the actual situation.). most of the heat loss that occurs in bd3550hfn,bd3551hfn,bd3552hfn is generated from the output nch fet. power loss is determined by the total v in -vo voltage and output current. be sure to c onfirm the system input and output voltage and the output current conditions in relation to the heat dissipation characteristics of the v in and vo in the design. bearing in mind that heat dissipation may vary substantially depending on the substrate employed (due to the power package incorporated in bd3550hfn,bd3551hfn,bd3552hfn) make certain to factor conditions such as substrate size into the thermal design. power consumption (w) = input voltage (vin)- output voltage (vo) (vo P vref) io(ave) example) where vin=1.8v, vo=1.2v, io(ave) = 1a, power consumption (w) = 1.8(v)-1.2(v) 1.0(a) = 0.6(w) calculation based on ambient temperature (ta) tj=ta+ j-a w 1-layer substrate (copper foil density 0.2%) 1-layer substrate (copper foil density 7%) 2-layer substrate (copper foil density 65%) substrate size: 70 70 1.6mm 3 (substrate with thermal via) reference values j-a:hson8 198.4 /w 92.4 /w 71.4 /w
13/16 input-output equival ent circuit diagram reference landing pattern (unit:mm) lead pitch e lead pitch mie landing length R l2 landing pitch b2 0.65 2.50 0.40 0.35 central pad length central pad pitch d3 e3 2.90 1.90 *it is recommended to design suitable for the actual application. vcc vo1 vo2 50k 1k 1k 350k 10k en nrcs vcc 1k 10k 1k 1k 1k 1k vcc 10k vin 1k vcc vfb 1k 100k 100k 20pf d3 mie e3 e b2 l2
14/16 operation notes 1. absolute maximum ratings an excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down the devices, thus making impossible to identify break ing mode, such as a short circuit or an open circuit. if any over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses. 2. connecting the power supply connector backward connecting of the power supply in reverse polarity can da mage ic. take precautions when connecting the power supply lines. an external direction diode can be added. 3. power supply lines please add a protection diode when a large inductance component is connected to the output te rminal, and reverse-polarity power is possible at startup or in output off condition. 4. gnd voltage the potential of gnd pin must be minimu m potential in all operating conditions. 5. thermal design use a thermal design that allows for a sufficient margin in light of the power dissipation (pd) in actual operating conditions. 6. inter-pin shorts and mounting errors use caution when positioning the ic for mounting on print ed circuit boards. the ic may be damaged if there is any connection error or if pins are shorted together. 7. actions in strong electromagnetic field use caution when using the ic in the presence of a strong electr omagnetic field as doing so may cause the ic to malfunction. 8. aso when using the ic, set the output transistor so that it does not exceed absolute maximum ratings or aso. 9. thermal shutdown circuit the ic incorporates a built-in thermal shutdown circuit (tsd ci rcuit). the thermal shutdown circuit (tsd circuit) is designed only to shut the ic off to prevent therma l runaway. it is not designed to protect the ic or guarantee it s operation. do not continue to use the ic after operating this circuit or use the ic in an environment where the operation of this circuit is assumed. tsd on temperature [c] (typ.) hysteresis temperature [c] (typ.) bd3550hfn,bd3551hfn,bd3552hfn 175 15 10. testing on application boards when testing the ic on an application board, connecting a capacito r to a pin with low impedance subjects the ic to stress. always discharge capacitors after each process or step. always turn the ic's power supply off before connecting it to or removing it from a jig or fixture during the inspection proces s. ground the ic during assembly st eps as an antistatic measure. use similar precaution when trans porting or storing the ic. output pin (example)
15/16 11. regarding input pin of the ic this monolithic ic contains p+ isolation and p substrate layers between adjacent el ements in order to keep them isolated. p-n junctions are formed at the intersection of these p layers wi th the n layers of other elem ents, creating a parasitic diode or transistor. for example, the relation between each potential is as follows: when gnd > pin a and gnd > pin b, the p-n j unction operates as a parasitic diode. when gnd > pin b, the p-n junction operates as a parasitic transistor. parasitic diodes can occur inevitable in the structure of the ic. t he operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physical dama ge. accordingly, methods by which parasitic diodes operate, such as applying a voltage that is lower than the gnd (p substrate) voltage to an input pin, should not be used. 12. ground wiring pattern. when using both small signal and large current gnd patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. be careful not to change the gnd wiring pattern of any external components, either. heat dissipation characteristics hson8 resistor transistor (npn) n n n p + p + p p substrate gnd parasitic element pin a n n p + p + p p substrate gnd parasitic element pin b c b e n gnd pin a p aras iti c element pin b other adjacent elements e b c gnd p aras iti c element (1) substrate (copper foil density: 0.2%?1-layer) j-a=198.4 /w (2) substrate (copper foil density: 7%?1-layer) j-a=92.4 /w (3) substrate (copper foil density: 65%?1-layer) j-a=71.4 /w power dissipation [pd] [w] 0 25 75 100 125 150 50 [ ] ambient temperature [ta] 1.0 0.5 0 2.0 1.5 (1) 0.63w (2) 1.35w (3) 1.75w
16/16 type designations (ordering information) b d 3 5 5 x - t r h product name package type tr emboss tape reel opposite draw-out side: 1 pin ? bd355x ? hfn : hson8 f n (unit:mm) embossed carrier tape tr (the direction is the 1pin of product is at the upper light when you hold reel on the left hand and you pull out the tape on the right hand) tape quantity direction of feed 3000 p cs reel 1pin x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x hson8 0.13 + 0.1 ? 0.05 4 3 2 1 5 6 7 8 3.00 0.2 2.80 0.2 2.90 0.2 0.475 0.32 0.10 0.65 0.6max. 1 2 3 4 (0.2) (1.8) (0.2) (0.30) (0.05) (2.2) (0.15) (0.45) 8 7 6 5 direction of feed when you order , please order in times the amount of package quantity. catalog no.08t416a '08.10 rohm ?
appendix1-rev3.0 thank you for your accessing to rohm product informations. more detail product informations and catalogs are available, please contact your nearest sales office. rohm customer support system the americas / europe / asia / japan contact us : webmaster@ rohm.co. jp www.rohm.com copyright ? 2008 rohm co.,ltd. 21 saiin mizosaki- cho, ukyo-ku, kyoto 615-8585, japan tel : +81-75-311-2121 fax : +81-75-315-0172 appendix notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of rohm co.,ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing rohm's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specifications, which can be obtained from rohm upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, rohm shall bear no respon- sibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the products. rohm does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by rohm and other parties. rohm shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products are not designed to be radiation tolerant. while rohm always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possi bility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. rohm shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which re quires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). rohm shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the f oreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law.

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